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SI3232PPT0-EVB
EVALUATION B O A R D F O R T H E Si3232 DU A L PROS LIC
Description
This document describes the operation of the Silicon Laboratories Si3232 Dual ProSLICTM device evaluation platform. The Dual ProSLIC evaluation platform is designed to provide observation of the ProSLIC's functionality. The Dual ProSLIC platform consists of a ProSLIC motherboard, an Si3232 daughter card (Si3232DC0-EVB), and the ProSLIC LINCTM software. The ProSLIC LINC software is a GUI-based program that can run in Microsoft Windows(R) environments. Equipment requirements: PC running Windows 95, 98, ME, NT, or 2000 5 V, 1 A power supply 3 V, 1 A power supply (optional) -24 V, 0.5 A power supply -75 V, 0.5 A power supply Balanced audio generator and analyzer (optional)
(e.g., Audio Precision System 2 and/or HP TIMS set and/or Wandel and Goltermann PCM-4)
Features
Silicon Laboratories Dual ProSLIC device All components necessary for linecard implementation Layout for optional secondary protections Control I/O through standard parallel port On-board oscillator for stand-alone operation PCM I/O set up for Audio Precision System 2 or Wandel and Goltermann PCM-4 Full access to PCM highway Daisy-chain connection for multiple boards Si3232 power selection for 3 or 5 V operation
Functional Block Diagram
VBHI, VBLO, +3 V, +5 V Power In Four-Wire Analog I/O Parallel Port
Si3232
Si3200
Si3200
Si3232DC0-EVB
Rev. 1.0 4/03
Copyright (c) 2003 by Silicon Laboratories
SI3232PPT0-EVB-10
SI3232PPT0-EVB
ProSLIC LINC Evaluation Software
The ProSLIC LINC software is an executable program that allows control and monitoring of the ProSLIC. It utilizes the primary LPT port of a standard PC to communicate to the ProSLIC's SPI port. To install the software, insert the Silicon Laboratories ProSLIC CD into the computer. The setup routine can be invoked by running the setup.exe program in the root directory of the CD. Invoking the ProSLIC LINC is achieved by double clicking the ProSLIC LINC icon. Refer to the ProSLIC LINC User Guide for software operation. PCLK frequency and controls the FS enable. See Table 1 for S2 settings. JP3 and JP4 select this internal clock source or an external PCM clock source. The ProSLIC motherboard has been designed with digital PCM interfaces (P2, P3, J8, and J11). These connections are not used with the Si3232 Dual ProSLIC. J9 and J10 allow access to the ProSLIC's clock inputs for connection to an actual telephone system's clocks. TIP and RING of the two-wire analog interface is present at the RJ-11 connectors, J1 and J11 of the Dual ProSLIC daughter card. The schematics of the ProSLIC motherboard are found in Figures 9, 10, and 11. Figure 9 shows the connections from the motherboard to the daughter card. Figure 10 illustrates the LPT port connection to the SPI drivers. The PCM highway and LED indicators are shown in Figure 11. The ProSLIC evaluation board is voltage programmable with specific jumper settings. JP1 selects 3 V for ProSLIC operation. JP2 selects 3 V or 5 V PCM source level compatibility. These should be placed on the expected setting. Power is connected to the ProSLIC at J2, J3 and J4. The 5 V is always required for the buffers, U2 and U3, to interface to the parallel port. The ProSLIC can be powered from 5 V or 3 V with the placement of a jumper on JP1. The Protection Return connections on J6 should be connected to an appropriate ground for TIP/RING fault testing. This return is tied to signal ground on-board though it has a dedicated trace for high current conditions. Serial control of the ProSLIC is achieved by toggling select bits of a standard parallel port. The parallel port connection is available at P1 and J1. Multiple dual ProSLIC cards can be daisy-chained by stacking the cards. Stack up to eight cards by aligning JS1-JS5 and pressing together. The ProSLIC LINC Software allows channel selection for RAM and register manipulation.
SI3232PPT0-EVB Dual ProSLIC Evaluation Board Description
The schematics for the Dual ProSLIC evaluation daughter card are shown in Figures 1 through 3. The schematic in Figure 1 shows the Dual ProSLIC linecard implementation. All circuitry pertaining to the telephony function of the Dual ProSLIC is found here. Four-wire analog is present on JP3 and JP4. Figure 2 contains a number of options for secondary fault protection. Secondary protection components can be selected for a given level of protection against expected faults. Figure 3 is the schematic that describes the serial control interface, daisy chain ports, and power supply filtering and connections. These schematics represent typical linefeed components for the ProSLIC. The layout of the Dual ProSLIC evaluation daughter card is found in Figures 4-8. Figure 4 shows the component placement while Figures 5 and 8 show the two layers of component interconnect. Figures 6 and 7 show the inner ground and VDD planes. The signal flow is four-wire analog on the left to two-wire analog on the right. Signal requirements for ProSLIC operation are PCLK (PCM clock), FS (frame sync), and Serial IO. The ProSLIC motherboard has a local oscillator with a programmable logic device to provide the ProSLIC PCLK and FS signals. The DIP switch (S2) sets the
2
Rev. 1.0
SI3232PPT0-EVB
SI3232PPT0-EVB Dual ProSLIC Evaluation Platform Setup
To prepare the Dual ProSLIC evaluation platform for use, perform the following steps:
1. Set power supplies to 3.3 V, 5 V, -24 V, and -75 V. 2. With these supplies off, connect them to J2, J3, and J4 corresponding to the silk screen designators. 3. Connect the PC's parallel port (LPT1) to P1 (or J1) using a 25 pin D male-to-male cable. 4. Select the on-board clock source or external clock source with JP3 and JP4. 5. TIP/RING connection can be made from the RJ-11s to a phone or telephony test equipment. 6. Invoke the ProSLIC LINC software. 7. Turn the power supplies on and press the ProSLIC motherboard reset button (S1). 8. Click the "Reinitialize" button in the ProSLIC LINC software panel.
The Dual ProSLIC is now ready to perform its linecard function. To achieve an end-to-end connection with 600 :
1. Verify that R11 is shorted. 2. Click RESET. 3. Click REINITIALIZE. 4. Click REGISTER SET. 5. Click Broadcast box. 6. Write "1" to LINEFEED register.
This connects the evaluation platform end-to-end per daughter card RF-11 connector pairs.
Table 1. On-Board PCLK Settings (S2)
S2-1,2,3 PCLK frequency 0,0,0 = 8.192 MHz 0,0,1 = 4.096 MHz 0,1,0 = 2.048 MHz 0,1,1 = 1.024 MHz 1,x,x = 512 kHz
Note: 1 = on.
S2-4 unused x
S2-5 unused x
S2-6 unused x
S2-7 unused x
S2-8 FS enable 0 = FS disabled 1 = FS enabled
Rev. 1.0
3
6 5 4 3 2 1
RJ-11 SMD
1
1
U1 C3 10n 100V TP5 TP6 TP7 TP8 GNDGNDGNDGND
1 1 1 1
C4 10n 100V
STIPDCa STIPACa SRINGACa SRINGDCa ITIPNa IRINGNa ITIPPa VDD1 GND1 IRINGPa THERMa VRXPa VRXNa VTXPa VTXNa BATSELa
64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49
R11 C11 C12 TP3 Tip B VDD
1
402k 4.7k 4.7k VRXNb 402k VRXPb CMLevel VRXPa VRXP VRXPb VTXNb VTXPb VTXPa VTXP VTXPb
VTXP VTXN
0.1u 100V X7R 0.1u 100V X7R
R13 R14 R12
17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32
STIPDCb STIPACb SRINGACb SRINGDCb ITIPNb IRINGNb ITIPPb VDD2 GND2 IRINGPb THERMb VCM VRXPb VRXNb VTXPb VTXNb
RJ-11 SMD
Ring B TP4
R16
40.2k
C31 0.1u 100V VBHI
C33 0.1u 100V VBLO
Si3200
GND
epad
Figure 1. Si3232DC0-EVB Evaluation Circuit (1 of 3)
VRXP VRXN
1
4
VDD JCP4 J1 TP1 Tip A Protection TIPa_ext TIPa TIPa RINGa VDD U2 CMLevel VTXP RINGa_ext RINGa Ring A TP2 C30 0.1u 100V VBHI C32 0.1u 100V VBLO
SI3232PPT0-EVB
1 2 3 4 5 6 7 8
TIP NC RING VBAT VBATH VBATL GND VDD
ITIPP ITIPN THERM IRINGP IRINGN NC NC BATSEL GND
16 15 14 13 12 11 10 9 epad
C2 C1 0.1u 100V X7R 0.1u 100V X7R
VRXP +5V VDD VBLO R6 R2 R4 R3 R1 40.2k VRXPa 402k VRXNa 4.7k 4.7k 402k TIPa_EXT VTXPa VTXNa DETn /RESET VBHI
Si3200
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25
26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50
VTXN VRXN
RINGa_EXT
con50_champ_m AMP 5-175473-6 J2
R5 R8 R7 C5 1u 6V C6 1u 6V R10 C15 C16 1u 6V R17 R18 R15 1u 6V
806k 182 182
40.2k 182 182 806k
C13 10n 100V
C14 10n 100V
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16
SVBATa RPOa RPIa RNIa RNOa CAPPa CAPMa QGND IREF CAPMb CAPPb RNOb RNIb RPIb RPOb SVBATb
Si3232
GPOa /CS SDITHRU SDI SDO SCLK VDD4 GND4 /INT PCLK GND3 VDD3 GPOb BATSELB FSYNC /RST
48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33
DETn /CS SDITHRU SDI SDO SCLK /INT PCLK
1 2
GPOa
Rev. 1.0
J11
J3
1 2
FSYNC /RESET
GPOb
Channel
2 4 6 2 4 6
VTXNa VTXN VTXNb VRXNa VRXN VRXNb
JP3
1 3 5 1 3 5
1 3 5 1 3 5
JP4
2 4 6 2 4 6
a b a b
6 5 4 3 2 1
Protection TIPb_ext TIPb TIPb RINGb
U3
RINGb_ext RINGb
1 2 3 4 5 6 7 8
TIP NC RING VBAT VBATH VBATL GND VDD
ITIPP ITIPN THERM IRINGP IRINGN NC NC BATSEL
16 15 14 13 12 11 10 9
JP2 SDO /CS PCLK 12 34 56 78 9 10 AUX Cntl
9 7 5 3 1 3 1 9 7 5 3 1 3 1 1 3
SCLK SDI
4 2
10 8 6 4 2
JS2
2 4 1 3 2 4
FSY NC
JS1
10 8 6 4 2
4 2
JP1 CONN HEADER 2x2/SM (Farside)
CONN SOCKET 5x2
CONN SOCKET 2x2/SM
SDITHRU VDD 1 3 5 7 9 1 3 5 7 9 VBLO VBHI
1 3 5 7 9
SDI
JS4 2 4 6 8 10 2 4 6 8 10
SDO SCLK /CS /INT PCLK FSYNC /RESET
JS3 9 7 5 3 1 9 7 5 3 1 10 8 6 4 2 10 8 6 4 2
CONN SOCKET 5x2
CONN SOCKET 5x2
2 4 6 8 10
Rev. 1.0
VDD C20 0.1u C21 0.1u C22 0.1u C23 0.1u C24 0.1u C25 0.1u
1 3 5 7 9 2 4 6 8 10
JS5 CONN SOCKET 5x2
SI3232PPT0-EVB
VBLO
C34 0.1u 100V
C35 0.1u 100V
Figure 2. Si3232DC0-EVB Evaluation Circuit (interconnect) (2 of 3)
5
c
c
6
RF1
SI3232PPT0-EVB
1
2
F1250T RF5
TIPa_ext NI TS250-130-RA D3 NI P0901SC RV1
TIPA
1 2
TIP
NC
6 5 4
VREF GND RING NC
D4 NI P0901SC VBHI
C36 0.1u 100V
3
c
B1101UC
RF6 RINGa_ext NI TS250-130-RA RF2 RINGA
1
2
F1250T RF11
1
2
F1250T RF15
TIPb_ext NI TS250-130-RA D13 NI P0901SC RV2
TIPB
1 2
TIP
NC
6 5 4
VREF GND RING NC
Rev. 1.0
RINGb_ext NI
D14 NI P0901SC VBHI
C37 0.1u 100V
3
c
B1101UC
RF16 RINGB TS250-130-RA
RF12
1
2
F1250T
* Optional protection devices: Battery tracking over voltage protection devices are required when using maximum battery voltage on Si3200. Fixed voltage thyristor protection devices, D3, D4, D13, D14 can be used in certain cases. The selection of the thyristor device voltage depends on the required battery voltage for ringing. The maximum clamp voltage for the device must be under the Si3200 maximum voltage. The minimum clamping voltage of the device must be above the maximum battery voltage. For example, the Teccor P0901SC is shown for applications that operate from a maximum negative battery of -72V. Over current devices should be selected for application requirements and over voltage protection device current limitations.
Figure 3. Si3232DC0-EVB Evaluation Circuit (protection) (3 of 3)
SI3232PPT0-EVB
Bill of Materials
Table 2. Si3232DC0-EVB Application Circuit
Component(s) C1, C2, C11, C12 C3, C4, C13, C14 C5, C15 C6, C16 C30-C33 C20-C25 R1, R2, R11, R12 R3, R4, R13, R14 R5, R15 R6, R16 R7, R8, R17, R18 R10 Value 100 nF, 100 V, X7R, 20% 10 nF, 100 V, X7R, 20% 1 F, 6.3 V, X7R, 20% 1 F, 6.3 V, X7R, 20% 0.1 F, 100 V, Y5V 0.1 F, 10 V, Y5V 402 k, 1/10 W, 1% 4.7 k, 1/10 W, 1% 806 k, 1/10 W, 1% 40.2 k, 1/10 W, 5% 182 , 1/10 W, 1% 40.2 k, 1/10 W, 1% Function Filter capacitors for TIP, RING ac sensing inputs. TIP/RING compensation capacitors. Low pass filter capacitors to stabilize common mode SLIC feedback loops. Low pass filter capacitors to stabilize differential SLIC feedback loops. Decoupling for battery voltage supply pins. Decoupling for analog and digital chip supply pins. Sense resistors for TIP and RING voltage sensing nodes. Sense resistors for TIP, RING ac sensing inputs. Sense resistor for battery voltage sensing nodes. Sets bias current for battery switching circuit. Bias resistors for internal transconductance amplifier. Generates a high accuracy reference current.
Table 3. Si3232DC0-EVB Protection Circuit
Component(s) C36, C37 D3, D4, D13, D14* RF1, RF2, RF11, RF12 RF5, RF6, RF15, RF16* RV1, RV2 Description 0.1 F, 100 V, Y5V Teccor P0721SC transient voltage suppressor Teccor F1250T, 250 V/1.25 A, TeleLink fuse Raychem TS-250-130-RA resettable fuse Teccor B1101UC Dual Negative BATTRAX SLIC Protector or Bourns TISP61089B Function/Comments Decoupling for B1101UC. Overvoltage protection (optional). Overcurrent protection. Overcurrent protection PTC (optional). Battery-tracking overvoltage protection.
*Note: Optional protection components not used on Si3232DC0-EVB. Usage depends on application.
Rev. 1.0
7
8 Rev. 1.0
SI3232PPT0-EVB
Figure 4. Si3232DC0-EVB Silkscreen
Rev. 1.0 9
Figure 5. Si3232DC0-EVB Component Side
SI3232PPT0-EVB
10 Rev. 1.0
SI3232PPT0-EVB
Figure 6. Si3232DC0-EVB Power
Rev. 1.0 11
Figure 7. Si3232DC0-EVB Ground
SI3232PPT0-EVB
12 Rev. 1.0
SI3232PPT0-EVB
Figure 8. Si3232DC0-EVB Solder Side
Power
LPT Port
4 2 10 8 6 4 2 4 2
JS1
10 8 6 4 2
JS2 JS3 CONN SOCKET 2x2
9 7 5 3 1
3 1
9 7 5 3 1
3 1
CONN SOCKET 5x2
+VIN
Power, Ground
SPI
JS4
VDD
External PCM
JS3 PCM
2 4 6 8 10
2 4 6 8 10
1 3 5 7 9
1 3 5 7 9
VBLO VBHI
SDI DIN TEST SDO SCLK /CS /INT DOUT PCLK DRX DTX FSYNC /RESET
9 7 5 3 1
9 7 5 3 1
10 8 6 4 2
10 8 6 4 2
CONN SOCKET 5x2 VBRNG VRNGSOURCE
CONN SOCKET 5x2
ProSLIC Motherboard
1 3 5 7 9 1 3 5 7 9
JS5 CONN SOCKET 5x2
Figure 9. ProSLIC Motherboard (ProSLIC IF)
2 4 6 8 10
2 4 6 8 10
Rev. 1.0 13
SI3232PPT0-EVB
8 7 6 5
8 7 6 5
U1 /RESET TEST /CS SDI DIN SCLK VDD
200k
8 7 6 5
1 2 3 4
1 2 3 4
TP D6
TP D5
/RESET TEST /CS SDI DIN SCLK
GND B8 B7 B6 B5 B4 B3 B2 B1 OEB VCCB VCCB
4245A
GND GND A8 A7 A6 A5 A4 A3 A2 A1 DIR VCCA
1 2 3 4
8 7 6 5
8 7 6 5
1 2 3 4
1 2 3 4
Ringing Battery High Battery Low Battery Common Common Common
1 2 3
VRNGSOURCE NC RNG Source Return
J2 +3V VBRNG VBHI L1 VBLO
J3
1 2 3
CON3
CON3
+3V 1 +5V 2 +Vin 3
Protection Return Protection Return Protection Return
1 2 3
3 21
EMI Filt D1 Zener 6.8V C12 0.1 uF 6Vmin C13 100uF 10Vmin
1 23
EMI Filt C14 100uF 10Vmin D2 Zener 6.8V
J5
J6
1 2 3
14
VDD +5V R1 R2 R3 200k P1 /RST /CS_IN SDI_IN SCLK_IN R6 C1 100 pF 470 C2 0.1 uF 6Vmin D7 J1 U2 OUT_EN D IN D5 D6 TEST_IN /STROBE /AUTOFD D0 ERROR D1 INIT D2 /SELECT D3 D4 D5 D6 D7 /ACK BU SY PAPEREND SELECT
SI3232PPT0-EVB
13 14 15 16 17 18 19 20 21 22 23 24
12 11 10 9 8 7 6 5 4 3 2 1
S1 Reset Push Button
Two Package Widths
R7 R5 10k NI R4 10k
DTX DOUT SDO /INT TEST
DTX DOUT SDO /INT TEST
13 14 15 16 17 18 19 20 21 22 23 24
GND B8 B7 B6 B5 B4 B3 B2 B1 OEB VCCB VCCB
4245A
GND GND A8 A7 A6 A5 A4 A3 A2 A1 DIR VCCA
12 11 10 9 8 7 6 5 4 3 2 1
SPARE DIGITAL OUT SDO_OUT /INT_OUT TEST _OUT
1 3 5 7 9 11 13 15 17 19 21 23 25
2 4 6 8 10 12 14 16 18 20 22 24 26
1 14 2 15 3 16 4 17 5 18 6 19 7 20 8 21 9 22 10 23 11 24 12 25 13
DB25F Parallel port
HEADER 13X2 Parallel Port Hdr
Two Package Widths
SDO_OUT
Rev. 1.0
CON3
+VIN
J4 +5V
+5V
VDD
C3 +5V VDD +3V JP1 0.1 uF 6Vmin 1-2 : 3V operation 2-3 : 5V operation
C4 0.1 uF 6Vmin
C5 0.1 uF 6Vmin
C6 0.1 uF 6Vmin
C7 0.1 uF 6Vmin
C8 0.1 uF 6Vmin
C9 0.1 uF 6Vmin
C10 0.1 uF 6Vmin
C11 0.1 uF 6Vmin
L2
CON3
CON3
1 2 3
3V or 5V oper VRNGSOURCE
Component Power Selection
Single point connection to ground plane
Ringing Source Input
Figure 10. ProSLIC Motherboard (LPT to SPI)
+5V +5V +3V
VDD
+5V
PCM bus
1 2 3
JP2
8 7 6 5
PCMVDD R8 330 C15
1-2 : 3V 2-3 : 5V
8 7 6 5
R9 330 D4
1 2 3 4
0.1 uF 6Vmin
D3 +5V
PCLK LED
1
OE VDD GND OUT
32.768MHz
8 5
U3
1 9 2 10 3 11 4 12 5 13 6 14 7 15 8
4
INTF SYNC JP6 U6 FPGA PLCC-44
12 34
EXTFSYNC EXTDRX EXTPCLK EXTDTX S2 DIP Switch
FS
/RESET EXTDRX FS
10 8 6 4 2
NI
9 7 5 3 1
DB15M To Audio Prec RX
P3
1 2 3 4 5 6 7 8 1 2 3 4 5 6 7 8
16 15 14 13 12 11 10 9
S1 S2 S3 S4 S5 S6 S7 S8 CLK
15 16 17 18 19 20 21 22 25 26 27 28 29 30 31 32 11 35 33 13 14 36 2
I/O0 I/O1 I/O2 I/O3 I/O4 I/O5 I/O6 I/O7 I/O8 I/O9 I/O10 I/O11 I/O12 I/O13 I/O14 I/O15
I/O16 I/O17 I/O18 I/O19 I/O20 I/O21 I/O22 I/O23 I/O24 I/O25 I/O26 I/O27 I/O28 I/O29 I/O30 I/O31
37 38 39 40 41 42 43 44 3 4 5 6 7 8 9 10 24
EXTDRX INTDRX EXTDTX INTDTX EXTFSYNC INTF SYNC EXTPCLK INTPCLK
1-2: Int 2-3: Ext
1 2 3
JP3
12 11 10 9 8 7 6 5 4 3 2 1
GND GND A8 A7 A6 A5 A4 A3 A2 A1 DIR VCCA
4245A
GND B8 B7 B6 B5 B4 B3 B2 B1 OEB VCCB VCCB
13 14 15 16 17 18 19 20 21 22 23 24
DRX FSYNC PCLK
VCC VCC
JP5
EXTFSYNC INTPCLK
PCLK
12 34 56 78 9 10
NI
Two Package Widths
R11 NI
1 9 2 10 3 11 4 12 5 13 6 14 7 15 8
SDI LED
U5
To ProSLICs
DTX/DRX loopback U4 PCK /CS LED SCLK LED /INT LED SDO LED SDI LED EXTDTX
1-2: Int 2-3: Ext
1 2 3
JP4
Y0 SDO/IN1 Y1/RESET Y2/SCLK ispEN SDI/IN0 MODE/IN2 GOE0/IN3
J8 EXTDRX
J9 EXTFSYNC
Omit Pin 5
EXTPCLK
+5V
J7 HEADER 8X1
12 11 10 9 8 7 6 5 4 3 2 1
GND GND A8 A7 A6 A5 A4 A3 A2 A1 DIR VCCA
4245A
GND B8 B7 B6 B5 B4 B3 B2 B1 OEB VCCB VCCB
13 14 15 16 17 18 19 20 21 22 23 24
/CS SCLK /INT SDO_OUT SDI DTX
} LED drive
1 23
GND GND
TEST_IN J13 NI
D7
D7 C16
EXTPCLK J10 J11
EXTDTX
C17 0.01 uF 6Vmin
8 7 6 5
Two Package Widths
R10 10k
2 1
0.1 uF 6Vmin
1 2 3 4
/RST LED
P2
FSY NC LED
DB15F To Audio Prec TX
SCLK LED
SDO LED
/INT LED
/CS LED
1 2 3 4
Rev. 1.0 15
SI3232PPT0-EVB
External PCM
On-board PCM Clocks
Figure 11. ProSLIC Motherboard (PCM)
SI3232PPT0-EVB
Document Change List
Revision 0.92 to Revision 1.0
"Functional Block Diagram" on page 1 updated. "SI3232PPT0-EVB Dual ProSLIC Evaluation Board Description" on page 2 updated. Figures 1 through 11 updated.
16
Rev. 1.0
SI3232PPT0-EVB
Notes:
Rev. 1.0
17
SI3232PPT0-EVB
Contact Information
Silicon Laboratories Inc. 4635 Boston Lane Austin, TX 78735 Tel: 1+(512) 416-8500 Fax: 1+(512) 416-9669 Toll Free: 1+(877) 444-3032 Email: productinfo@silabs.com Internet: www.silabs.com
The information in this document is believed to be accurate in all respects at the time of publication but is subject to change without notice. Silicon Laboratories assumes no responsibility for errors and omissions, and disclaims responsibility for any consequences resulting from the use of information included herein. Additionally, Silicon Laboratories assumes no responsibility for the functioning of undescribed features or parameters. Silicon Laboratories reserves the right to make changes without further notice. Silicon Laboratories makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does Silicon Laboratories assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation consequential or incidental damages. Silicon Laboratories products are not designed, intended, or authorized for use in applications intended to support or sustain life, or for any other application in which the failure of the Silicon Laboratories product could create a situation where personal injury or death may occur. Should Buyer purchase or use Silicon Laboratories products for any such unintended or unauthorized application, Buyer shall indemnify and hold Silicon Laboratories harmless against all claims and damages. Silicon Laboratories, Silicon Labs, ProSLIC, and LINC are trademarks of Silicon Laboratories Inc. Other products or brandnames mentioned herein are trademarks or registered trademarks of their respective holders.
18
Rev. 1.0

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